This invention relates to a phase-lock loop including a tristate phase detector and is more particularly described as a tristate phase-lock loop arranged to avoid locking on the wrong frequency when a long string of zeros, or a sequence containing sparse ones, is received.
In a T1 transmission system, information is encoded as ones and zeros. Ones are represented by alternating positive and negative pulses. Zeros are represented as zero volts. This T1 signal format is called a bipolar alternate mark inversion (AMI) signal.
Along the cable, regenerators are used to boost the signals and improve the transmission characteristics of the system. Each regenerator receives the sequence of digital signals, amplifies, reshapes, and retimes the sequence of digital signals before retransmitting them along the cable. Retiming is accomplished by a clock signal which is generated in the regenerator in response to information contained in the received sequence of digital signals. The regenerator function also is used at the receiving terminals of a T1 transmission system.
A T1 terminal includes a receive converter device for extracting a 1.544 MHz clock signal from the received sequence of digital signals. Desired, or acceptable, clock signals have a frequency which is within a narrow range of frequencies centered at 1.544 MHz. The receive converter uses a phase-lock loop, including a phase detector, a low pass loop filter and a voltage-controlled oscillator (VCO), to recover the clock signal. The voltage-controlled oscillator generates the recovered clock signal at a frequency that varies in response to the magnitude of a tuning control signal voltage applied to the tuning control terminal of the VCO. The phase detector compares the received sequence of digital signals with the VCO clock output signal and produces a control signal having a magnitude which is proportional to the difference between the phases of the received sequence of digital signals and of the VCO clock output signal. The loop filter smooths the control signal into the tuning control signal before it is applied to the tuning control terminal of the VCO.
In circumstances in which the received sequence of digital signals includes all ones, the energy in the rectified signal spectrum is concentrated substantially more at the frequency of 1.544 MHz than at any other frequency. Automatic recovery of the clock signal at 1.544 MHz is easy under such circumstances.
When the received sequence of digital signals includes sparse ones, energy in the rectified signal spectrum is spread into several different frequencies. Energy is more concentrated at frequencies such as 1.16 MHz and 1.352 MHz than at 1.544 MHz when the sparse ones are being received. Accordingly, there is ambiguity in automatically recovering the correct clock frequency, and the VCO clock output signal frequency will not necessarily lock-on the desired 1.544 MHz. Instead the phase-lock loop may lock on a frequency other than close to 1.544 MHz.
Jitter may cause bit errors in the retimed digital signals. If the resulting bit error rate rises too high, it causes a severe degradation of the transmission system performance.
To avoid jitter, a tristate phase detector arrangement is used in the receive converter for opening the switch in the output lead of the tristate phase detector from the loop filter when each zero is received. When that switch is opened, the VCO is controlled by the preexisting tuning control voltage. Once lock is achieved with the tristate phase detector arrangement, the preexisting tuning control voltage causes the VCO to continue producing an output clock signal at the frequency where it is locked even though a string of zeros is received. The two pass loop filter is designed to retain its charge and, therefore, the preexisting control voltage for a time equal to the duration required for the occurrence of the maximum allowable string of consecutive zeros. If the VCO has been locked on 1.544 MHz, it will continue to produce that frequency because the tristate phase detector output is open circuited while zeros are being received. If, on the other hand, the VCO has already been locked on a different frequency because an undesirable tuning control voltage exists, then it will continue to produce that different frequency while sparse ones are being received.
This presents no particular problem while the T1 system is operating under normal conditions because once the phase-lock loop is locked to a frequency within the acceptable range near 1.544 MHz, the system will remain locked on that frequency. However, a problem may arise when the T1 system is first started up or when the T1 system has been operated on standby states and is switched into active service. At such times, the VCO tuning control signal voltage may not be at a value for causing the VCO to produce the clock output near 1.544 MHz. When the tristate phase detector output is opened in response to received zeros while the VCO tuning control signal voltage is at an undesired magnitude, the tuning control signal voltage stays at the wrong voltage, and the clock output from the VCO continues to be falsely locked at a frequency substantially different than the desired 1.544 MHz. This is called the false lock problem.
When the VCO produces clock output at a frequency other than a frequency with the desired range near 1.544 MHz, the regenerator will not operate, and the sequence of digital signals will not be processed at all.
This problem of false locking might be overcome by simply reducing the pull-in, or acquisition, range of the phase-lock loop; however, it is likely that such a solution will undesirably limit the amount of VCO drift, caused by temperature changes and component aging, which can be accommodated by the phase-lock loop during the lifetime of operation of the T1 system.
The problem also might be overcome by preventing the output switch in the tristate phase detector from switching open upon the receipt of every input zero. Instead the output switch can be left closed and input zeros counted until there are three or four zeros in an eight bit word. At that time the output switch of the tristate phase detector would be opened for every zero until the end of the word.